1. Field of the Invention
The present invention relates generally to first-in first-out (FIFO) buffers, and more particularly, to digital FIFO buffers for use with Single-Flux-Quantum (SFQ) superconductor integrated circuits for a physical-back-pressure mechanism.
2. Discussion of the Related Art
As a result of recent developments in superconductor technology, superconductor devices based on the Josephson effect are replacing conventional devices based on semiconductor technology for high performance and low power. The superconductor devices are well known as the ultimate high-speed, low-power digital logic family and are scalable to very-large scale integrated (VLSI) circuits. Digital circuits that employ superconductor devices and are fabricated using present circuit fabrication technology operate at clock rates ranging between 10-100 GHz. However, due to the high clock rates of superconductor devices, clock skew, clock jitter, and signal-propagation latency may often be larger than the clock period in the superconductor integrated circuits. These factors prevent cross-chip and chip-to-chip communication of such devices and lead to erroneous results.
The use of a first-in first-out (FIFO) buffer memory provides a well-known solution to achieve high data rates between incoherent synchronous circuits in the presence of large latency. The article “NbN Circuits and Packaging for 10 Kelvin IR Focal Plane Array Sensor Signal Processing,” IEEE Trans. on Appl. Suppercon., vol.9, pp. 4357-4360, June 1999 discloses a FIFO buffer that uses the MVTL superconducting logic family. However, the device disclosed in this article is physically large and operates in the 1 GHz regime, which is not suitable for SFQ superconductor devices operating in the 10-100 GHz regime. Also, an SFQ-based FIFO buffer that uses a similar logic synthesis would be physically too large, complex, and slow for most applications using SFQ superconducting logic.
What is needed is a FIFO buffer that is suitable for SFQ superconductive circuits which operate in the 10-100 GHz regime. Therefore, it is an object of the present invention to provide an SFQ-based FIFO buffer that enables high data rate, cross-chip and chip-to-chip communication for the superconductive circuits using SFQ logic.